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UVM verification of memory controller - open to bidding

Need someone to verify a memory controller using UVM environment. CAN bus is used as a memory cycle initiator and write/read burst transactions need to be verified.

Habilidades: FPGA, Perl, Shell Script, Verilog / VHDL, Very-large-scale integration (VLSI)

Acerca do Empregador:
( 0 comentários ) United States

ID do Projeto: #15695560

5 freelancers estão ofertando em média $375 para esse trabalho

$555 USD in 3 dias
(6 Comentários)
5.6
raulbehl

Hello! Please check my reviews and profile to know more about me and my work. Thank you! Relevant skills and experience Verilog 4+ years UVM 2+ years

$222 USD in 7 dias
(59 Comentários)
5.7
mingxiao2008

Dear Sir I read your proposal and that is good job for me I have these skills : Verilog / VHDL, Very-large-scale integration (VLSI) You can visit [login to view URL] , then you can see my past work for 2 years Mais

$155 USD in 3 dias
(0 Comentários)
0.0
FreelancerJoe15

I am doing this work on daily basis in my company projects and this can be done easily by me and with 100 % efficiency. Relevant Skills and Experience UVM, System Verilog, CAN Proposed Milestones $200 USD - After 50% Mais

$277 USD in 2 dias
(0 Comentários)
0.0
jliew888

I'd been working as UVM verification engineer for more than 15 years. The project that I'd been working ranging from block level such as MAC, PCIe PHY, MIPI to million gate count of SOC. Relevant Skills and Experience Mais

$666 USD in 5 dias
(0 Comentários)
0.0