hi i am student in turkey and i have a project which i cant do it.
basic ALU design with verilog. 32 bits full adder, substruction, negate , left-rigt shift,left-right rot, like that with spartan 3e starter [url removed, login to view] screen must show the result. code may not use like a=b+c this is for my graduation so if you can this program i will show my teacher then maybe we can change something you must support me like 15 days i will give my files but my theacher said " this is too simple make someting better" so you must better thing ok thats all i guess :) sorry for the writing mistake english is not my native language.
Visit my profile to see my much experience and knowledge on FPGA design using Verilog or VHDL. Please contact me and I will do it for you with an acceptable price. Thanks.
5 freelancers estão ofertando em média $82 para este trabalho
i am a computer engineering final year student. i have designed a processor in verilog. if interested, you can contact me on skype id: daniyalkhan50