verilog ALU design -- 2

hi i am student in turkey and i have a project which i cant do it.

basic ALU design with verilog. 32 bits full adder, substruction, negate , left-rigt shift,left-right rot, like that with spartan 3e starter [url removed, login to view] screen must show the result. code may not use like a=b+c this is for my graduation so if you can this program i will show my teacher then maybe we can change something you must support me like 15 days i will give my files but my theacher said " this is too simple make someting better" so you must better thing ok thats all i guess :) sorry for the writing mistake english is not my native language.

Habilidades: Verilog / VHDL

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Acerca do Empregador:
( 1 comentário ) istanbul, Turkey

ID do Projeto: #6843736

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Visit my profile to see my much experience and knowledge on FPGA design using Verilog or VHDL. Please contact me and I will do it for you with an acceptable price. Thanks.

$50 USD em 3 dias
(24 Comentários)

5 freelancers estão ofertando em média $82 para esse trabalho


Hi, I was waiting you to create the milestone so i start work , I hope you award me the project as discussed, waiting your reply Best Regards

$150 USD em 1 dia
(122 Comentários)

Hi I can design this ALU in just one or two hour With all the operations you suggested. Thanks SK

$50 USD in 3 dias
(7 Comentários)

I am working as Lab Engineer at FAST National University Pakistan, in Electrical Department, I have conducted the followings Labs, and also supervised Projects related to these labs. 1. Circuit Analysis and Design Mais

$50 USD in 2 dias
(3 Comentários)

i am a computer engineering final year student. i have designed a processor in verilog. if interested, you can contact me on skype id: daniyalkhan50

$111 USD in 15 dias
(0 Comentários)