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VHDL model of a direct map instruction cache

Implement, test and submit uncompressed file for aVHDL model of a direct map instruction cache with the following properties:

1. Total cache size is 4K bytes.

2. Block size = 1 instruction = 2 bytes.

3. Can either read or write one instruction in one clock cycle. Inputs change on rising edge of clock, outputs change on the next rising edge of the clock.

4. Assume all data and instruction addresses are aligned. This means that each instruction address is divisible by 2 since the size of an instruction is 2 bytes.

5. Inputs: 16 bits next PC value, 1 bit Read enable, 1 bit write enable

6. Output: 1 bit hit signal (1 = hit, 0 = miss)

7. Input/Output 16 bits instruction

Habilidades: Verilog / VHDL

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( 0 comentários ) Beirut, Lebanon

ID do Projeto: #5090010

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ahmedmohamed85

Dear sir, I have more than 5 years experience in digital design using vhdl, please check my profile to be sure that i can do it

$35 USD em 1 dia
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