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VHDL Project, register file

(Find the attached file)

Implement, test and submit uncompressed file for aVHDL model of a register file with the following properties:

1. Number of entries: 16 registers.

2. Data size: 16 bits per entry.

3. read and write latency: one cycle.

3. Two read ports, data output on the following rising edge of the clock.

5. One write port, data written on the following rising edge of the clock.

6. Data bypass from write port to either or both read ports when register written is the same as the register being read.

7. State after reset: all registers contain zero.

8. You are allowed to use a process since this is a storage array.

Habilidades: Verilog / VHDL

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( 0 comentários ) Beirut, Lebanon

ID do Projeto: #5120329

1 freelancer está ofertando em média $25 para este trabalho

zebrosweb

hi we thoroughly read your requirements from the attachment file. we can deliver as per your requirements. code should be in VHDL only also well commented and short notes will be provided to you. clear tech s Mais

$25 USD in 3 dias
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