• The Design Task is the systems design and test of a prototype Serial Data Packet System.
• The system will be developed as a VHDL model using Xilinx ISE WebPack Version 14.5 that
includes the use of the Xilinx iSim simulation tools for design verification.
• The design will be implemented on a self contained Xilinx/Digilent Spartan 3 XC3S200 FPGA
board to allow demonstration of a working system.