VHDL test procedure and test bench implementation

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VHDL test procedure and test bench implementation

Verilog / VHDL FPGA Engenharia Engenharia Elétrica Matlab and Mathematica

ID do Projeto: #34687469

Sobre o projeto

5 propostas Projeto remoto Ativo em 1 ano atrás

5 freelancers estão ofertando em média ₹25000 nesse trabalho

athulb

Hi client, Thank you for taking time to read my proposal. You are welcome review my profile to know more information. I have 4 years of experience in VHDL. Im familer with making counter, up counter , download coun Mais

₹25000 INR in 7 dias
(13 Comentários)
3.8
nikitaberezin

I'm verification engineer with 10 years of experience. Will provide good level of testbench for your design.

₹12500 INR in 7 dias
(2 Comentários)
2.9
nivashDVE

Hi, I am Senior verification Engineer and currently I have 4 year experience on ASIC/FPGA ,VHDL . I developed Test Bench for AXI interconnect , APB and SPI bridge from scratch . I developed system verilog assertion f Mais

₹25000 INR in 7 dias
(0 Comentários)
0.0
grapessoft

Hi Greetings! I am available right now for the project discussion and can start the project on an immediate basis. I have understood your project requirement I have7++ experience in design and development. I can ha Mais

₹37500 INR in 7 dias
(0 Comentários)
0.0