Vivado HLS fixed point code optimization

1. Vivado HLS fixed code optimization

2. Introduction of parallelism and pipeling

3. c-simulation, synthesis and RTL-C cosim verification

4. IP generation in Vivado HLS

5. Intergration of IP generated in HLS in Verilog code

Habilidades: Verilog / VHDL

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Acerca do Empregador:
( 1 comentário ) Hyderabad, India

ID do Projeto: #18952010

1 freelancer está oferecendo em média ₹12500 para esse trabalho


Dear Employer, I'm interested in your vivado hls task. I have 7 +years of experience in Electrical Engineering. I have the 2018 version. Contact me for further details. Regards,

₹12500 INR em 1 dia
(4 Comentários)