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Write some Software(degital alarm clock using vhdl)

My fpga board is de2(altera).i need to write vhdl code in this board. My project name is digital alarm clock using vhdl.

Time need to display on the lcd and stop watch need to display on the 7segments display. Plz help me

Habilidades: Verilog / VHDL

Ver mais: vhdl and verilog, write some code, vhdl, vhdl fpga, verilog vhdl, fpga vhdl, fpga verilog/vhdl, altera, alarm, code code alarm clock, clock alarm vhdl code, vhdl digital alarm clock, digital alarm clock using verilog, digital clock code using verilog, lcd verilog code fpga, alarm code vhdl, digital watch, alarm clock using vhdl, verilog write, digital alarm clock verilog, digital clock alarm verilog, fpga alarm clock, digital vhdl code, alarm clock vhdl, vhdl alarm clock code

Acerca do Empregador:
( 1 comentário ) Woodlands, Singapore

ID do Projeto: #6834346

Premiar a:

ahmedmohamed85

Dear sir I have more than 7 years experience in digital design using vhdl, also I have the de2 board, I am very interested in working on your project

$250 SGD em 12 dias
(119 Avaliações)
6.9

9 freelancers estão ofertando em média $95 para este trabalho

loi09dt1

I had the code now. please contact me and i will give you right now. so timely manner. Thanks. I had the code now. please contact me and i will give you right now. so timely manner. Thanks.

$50 SGD in 0 dias
(21 Comentários)
4.7
shobhitkapoor

Hi I am having 10 years of experience in design and verification, i can design clock witb alarm in few hours itself. Please let me know how to take this further.

$45 SGD em 1 dia
(6 Comentários)
4.1
zarnescugeorge

I can help you right away! Please send me a message to talk about it! Have a nice day! .

$56 SGD in 0 dias
(8 Comentários)
3.8
uetian09ee506

I am working as Lab Engineer at FAST National University Pakistan, in Electrical Department, I have conducted the followings Labs, and also supervised Projects related to these labs. 1. Circuit Analysis and Design Mais

$50 SGD em 1 dia
(2 Comentários)
2.2
miki28

Hello. My name is Milos Sapic and I am a Electronics engineer with experience in Digital desigen, i have experience with : Xilinx ISE, Active-HDL, Quartus II 13.0, Nios II 13.0, Qsys you can see in my portfolio. Plea Mais

$200 SGD in 3 dias
(0 Comentários)
0.0
SANGITAR

We possess the Altera DE2 board with cyclone 2 FPGA, i am ready to take on the task, pls visit [url removed, login to view] to know more about us.

$88 SGD em 1 dia
(0 Comentários)
0.0
yasith1991

This is a really easy project. I have the altera board and I can send you the code. Is it okay if I write my code in verilog because I'm really familiar with it. But I can code in VHDL. If you are interested please co Mais

$31 SGD in 3 dias
(0 Comentários)
0.0
rameshsundar82

I already completed this project I can give this to u in. cheap cost

$83 SGD em 1 dia
(0 Comentários)
0.0