Imagem de perfil de botondkireivw
Bandeira de Romania Cluj Napoca, Romania
Membro desde 12 de junho de 2008
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Design services since 2005 in electronics and related domains: VHDL/Verilog based digital design, functional and timing verification, audio/video signal processing.
$15 USD/hr
35 comentários
  • 84%Trabalhos Concluídos
  • 98%No orçamento
  • 98%No Prazo
  • 32%Taxa de Recontratação


Comentários recentes

  • image of tweedz Project 6637936 has been deleted $28.00 SGD

    “Timely completion, courteous and helpful (:”

  • image of worldcitizen324 verilog and vhdl assignment $40.00 USD

    “Good freelancer, will hire again.”

  • image of assignmentshelp Signals and Systems-2 $25.00 USD

    “Thanks for your help !!”

  • image of assignmentshelp Verilog and CPU processor $50.00 USD

    “Thanks for your help. Really appreciate it.”

  • image of vladeg XILINX FPGA + 16x2 LCD + IIC bus $60.00 USD

    “BEWARE! He stole my money and send dummy non-working code in return. His words: "I'm used to bill $15/hour. This is the code written in 4-5 hours, this is what you get for $60" Also gave me his inadequate demand: called me "middle man", and said that I should meet him with someone else, who is above me, if I want the project to be completed. I still don't understand what the hell his problem is. It was his bid to make the job for 60USD in 5 hours. I have received the dummy code only after one month, by the way. It was my fault to release milestone before he finish. I thought made it will make him work faster. Completely opposite happened. Also his response rate is 1 from 5 emails. Very hard to communicate with him.”

  • image of caius9090 Digital Signal Processing (DSP) Problem $42.50 USD

    “Rating: 5.0/5.0”


  • DSP
  • Digital Electronics Level 1
  • VLSI Level 1


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