shreyasvp

Shreyas Vijay Parnerkar Education: Masters Electrical Engineering, May 2010 University of Wisconsin-Madison GPA: 3.6/4.00 Independent Study & Thesis: Dynamic timing analysis of circuits with multiple inputs switching, false path and multi cycle path identification. Course Work: Digital Design & Synthesis (ECE 551), Introduction to Computer Architecture (ECE 552), Testing and Testable Design of Digital Systems (ECE 553) Design Automation of Digital Systems (ECE 556) VLSI Array for DSP Structures (ECE 734) Advanced Independent Study (ECE 999) Bachelor of Engineering, Electronics and Telecommunication August 2007 Pune Vidyarthi Griha's College of Engineering and Technology, Pune, INDIA Overall GPA: 3.78/4.00 Major GPA: 3.78/4.00 10th in the merit list of University of Pune, BE (Electronics and Tele-Communication) Research Interests: ü Digital Design, VLSI Design, VLSI CAD with focus on CAD tools and algorithm development. ü I am interested in DSP algorithm implementations for various platforms like FPGA, ASICs using standard cell library and full custom ASICs. I am interested in developing hardware optimizations for DSP algorithms. Work Experience: · Research Intern : June 2009 - August 2009 Tata Consultancy Services Innovation Labs, Kolkata, India Working with the R&D Team for implementation of a real time radio simulator for 3GPP LTE using cloud computing. The project is entirely implemented using Matlab. My contribution includes working on parallel processing using cloud computing. The focus is initially use our own private cloud using the MPI (message passing interface)implementation for high performance computing (parallel processing)so as to make it compatible with Enterprise clouds. · Project Assistant: Web Application Developer, Sept 2008 – May 2009 Professor Dr. Daniel Noguera, Noguera’s Research Group, Civil and Environmental Engineering, University of Wisconsin, Madison, WI 1. Developing a Web application for thermodynamic analysis of Fluorescent in situ hybridization using Java, JSP and Matlab. 2. Includes development of GUI and the Backend for the webpage and hosting the webpage on our own server. Tomcat web-server is used for the deployment of the website. · Project Assistant, Sept 2008 – May 2009 Dr. Bormin Huang (Assistant Research Scientist) Space Science and Engineering Center, University of Wisconsin, Madison 1. FPGA implementation of LAIS-LUT Algorithm for Hyper-spectral Imagery. 2. Implemented "Minimum Redundancy Prefix coding" for Data Compression using Xilinx FPGA. · Assistant Software Engineer, Oct 2007 – Apr 2008 Tata Consultancy Services Limited, Kolkata, India 1. Worked as part of the research and development team of the Embedded Systems Group. 2. Developed algorithms for hardware implementation of IEEE 802.16e, Mobile WiMAX standard. 3. Implemented the algorithms using C programming. 4. Assisted my seniors for its DSP implementation using cross compilers. 5. Completed a project in Tata Consultancy Services of developing a website of an Automobile Company to maintain records of sales, spare parts, servicing using JSP, Servlets, HTML, Java Script and Oracle 9i. Database was created and maintained using Oracle 9i. 6. Underwent training on Linux, Shell scripting on Linux, Core Java, J2EE (JSP, Servlets) and Oracle 9 including HTML, Scripting languages like Java Script, VBScipt. Hardware Skills Ø Microcontrollers like 89C51 Rd2, ARM (Philips LPC 21xx series), Micro-processors like 8086, 80386. Ø NVIDIA GPU. Ø Xilinx Spartan and Virtex FPGAs, Actel’s Pro ASIC PLUS FPGAs and Altera’s Stratix III FPGAs. Ø Various sensors like IR transmitter receiver, photo sensors. Ø Computer Networking Devices (Hubs, Switches, Modems) Software Skills v Programming Languages Ø Verilog, VHDL, Matlab, CUDA Ø C Programming for Microcontrollers (8051, ARM) Ø Assembly Language (8051, 8086, 80386) Ø RTOS programming using ¼COS Ø Shell Scripting, C Programming, Core Java, J2EE, Oracle 9i, VBScript, VB .NET using Visual Studio 2006, Java Script, HTML, CSS. v Software Tools Ø Matlab, Simulation software like Multisim, Electronics Workbench, Micro-Wind 3.1 (CMOS Design) Ø Synopsys Design Vision, TestCAD, Actel’s Libero IDE, Xilinx ISE, Altera’s Quartus. (FPGA & Standard Cell Library design) Ø Eclipse, Netbeans, Microsoft Access, MySQL, MS Office, Oracle 9i. Ø NVIDIA CUDA Profiler. v Operating Systems Ø Microsoft Windows Ø Unix, Linux (Red Hat, Ubuntu) Academic Projects: Master’s Project: Ø Design & Synthesis of Calibrated Temperature IC A calibrated temperature IC was coded using Verilog Hardware description language and synthesized using the “Synopsys Design Vision” tool. Pre Synthesis and Post Synthesis simulations were done and the design was functionally verified. Ø Design and implementation of WISC-F08 WISC-F08 was a 16-bit computer with load store architecture and fifteen instructions, which was implemented using Altera Quartus II. It had a 64 word data cache implemented using write-back scheme and 5 stage pipelining. Ø Test Generation, Diagnosis and Partial Scan The first part of the project dealt with the generation of an efficient test set for a given combinational circuit using “TESTCAD” toolset and also “Fault detection and diagnosis” of four circuits using the toolset. The second part dealt with usage of partial scan technique for a sequential circuit without compromising on the fault coverage. Ø Global Routing. The project is a VLSI-CAD project. The aim is to read benchmarks circuits to come up with the global routing solution for the nets. The first part of the project deals with breaking multi terminal nets into two terminal nets using “FLUTE” and then formulate an Integer Linear Programming problem and solve it using CPLEX to route the 2 terminal nets. It also involves post processing for un-routed nets. The project is implemented using Java programming. Ø Memory and Runtime Efficient Image Texture Classification using NVIDIA GPU. The project was an individual project. The focus was to accelerate Image texture classification using NVIDIA GPU. The project was implemented using CUDA. The time consuming part of the code was offloaded to GPU (NVIDIA Quadro NVS 290) and a speed up of about 100x was achieved compared to its implementation in Matlab. Undergraduate Projects: Ø VLSI Implementation of Color Graphics LCD Controller. Ø DC Motor Control using micro-controller (89C51Rd2) and Infra Red Remote Control. Other Information: v I secured a place (10th Rank) in the merit list of University of Pune for Bachelor of Engineering (Electronics and Telecommunication) degree. I stood second in the entire college among all faculties in the first year of engineering and again stood second in the third and fourth (final) year of engineering in my Electronics and Telecommunication department. I have consistently secured first class with distinction in all 8semesters of my engineering course. v I have received a certificate from Actel Corporation, USA for “Proficiency in FPGA Design” for my final year Project. v I served as an Executive Committee Member of Science Forum during my under graduation.