sridharan48
sridharan48
- N/ATrabalhos concluídos
- N/ANo Orçamento
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HIGH SPEED ANALOG DESIGN ENGINEER
Oct 2015Responsible for developing high speed OPAmp circuits in ADC Responsible to designing ADC backend stages Responsible for developing of clocking scheme of Dual ADC Responsible to designing of LVDS
PROJECT ASSOCIATE
Nov 2014 - Oct 2015 (11 months)Responsible for developing high speed inductor based PLL circuits Responsible for schematic design as well as layout of sub1V Bandgap and V2I Involved in layout design of digital blocks in high speed PLL Responsible for all the extracted simulation of PLL and Bandgap Involved in ADC extracted simulation
ANALOG CIRCUIT DESIGN ENGINEER
Oct 2012 - Oct 2014 (2 years)Responsible for developing high performance PLL circuits by using advanced deep-submicron fabrication technologies Handle the task of creating new topology PLL circuits as well as provide support for circuit integration Debugged and troubleshoot PLL blocks Developing and performing circuit design in 55nm to 28nm CMOS process technologies Worked with the layout designers to finalize the performance of the post layout
Educação
B.E in Electronics and communication Engineering
2008 - 2012 (4 years)Verificações
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