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Electronics Verilog / VHDL
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Ram P.

@vrpsachin

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M.S. Student NUS, Past: ASIC VERIFICATION ENGINEER

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India (11:22 AM)

Joined on August 26, 2011

HVLs: Systemverilog, VMM, UVM, OVM Scripting with PERL and PYTHON. Std Protocols: AHB, AXI, APB, UART, ITU-T G711 Processor Knowledge: ARM Cortex M4, ARM Cortex A5, BLACKFIN, SHARC

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Education

B.Tech

2007 - 2011

4 years

Flag of

India

2007 - 2011

4 years

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