Yana T. Profile

5,0

(3 avaliações)

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$20 USD / hora

pontianak,

indonesia

$20 USD / hora

No momento são 7:55 AM aqui

Entrou no Freelancer em maio 20, 2015

0 Recomendações

Yana T.

@yanatejaip5s

5,0

(3 avaliações)

3,0

$20 USD / hora

pontianak,

indonesia

$20 USD / hora

100%

Trabalhos Concluídos

100%

Dentro do Orçamento

100%

No Prazo

N/A

Taxa de Recontratação

RTL Design and Verification Engineer

Experienced as a Researcher with RTL Design and Verification and the used to some EDA Tools such as MATLAB, C Programming, Linux, Verilog, VHDL, FPGA PYNQ Z2 SoC Development Board, Physical IC Design with Pyxis Mentor Graphics & Cadence Design System, Synopsys VCS, Synopsys Astro, Eagle, Proteus, LTSpice Simulation Software & Microcontroller such as Arduino, ESP8266 & ESP32

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Itens de Portfólio

Synopsys Astro is the Automatic Place and Route (PnR) tool from Synopsys. It takes synthesized gate-level netlist and a standard cell library as input, then produces layout as an output. Synopsys Astro can also perform verification and generate back-annotation scripts. Besides that it is for Clock Tree Synthesis(CTS), PnR, Design For Manufacturing (DFM), Design Rule Check (DRC) and Layout Vs Schematic (LVS)

Back End Implementation of Basic Arithmetic Operation CNN

This CNN architecture give an instruction in the final output using maximum value detection as an activation function whether the input is horizontal or vertical with image classification using edge detection. The architecture can detect image classification input whether it vertical or horizontal and do the control. If it detect vertical so it will do indata1 + indata2 and if it detect horizontal it will do the indata1 x indata2. This architecture need bigger area but it can run in high speed and produce high throughput, there is no hold time negative slack and setup time negative slack as well

Basic Arithmetic Operation Controller with CNN

The Aim of this design is to ensure that the CMFB will give feedback or response to the Folded Cascode Amplifier to do some correction of DC output for the output of amplifier. According to the reference on the lecture, the output of the Folded Cascode Amplifier will be half of the vdd or Vref = Vdd/2. The results shows that it bring the output to the half of Vdd for about 900 mV, it have a 41.98 dB DC gain and then it can be say that the circuit is stable because having positive 79.39° phase margin

Design of a Folded Cascode with Common Mode Feedback (CMFB)

This project presents a voltage controller oscillator with CMOS transistor. The output of this circuit will be oscillate due to control of a voltage. The CMOS VCO will be run in the target frequency of 2.6GHz for the output voltage, have a low power consumption due to the low current of the drain it’s about ≤ 6.3mA in the drain CMOS current and have an enough large output power for about more than 4dbm

Design of Circuit CMOS VCO with 180nm Technology

This exploration project seeks to renew and make new innovations for the realization of applied craft work in Indonesia by combining textile craft science with exploration techniques that focus on the stylization of archipelago ornaments, laser cut techniques, several surface textile exploration techniques as well as electronic scientific exploration, namely a series of LEDs circuits

Exploration of Central Java Cultural Motives in Interior Pro

The system created is an angular velocity measuring device from a rotating motor with an infrared sensor. The output of sensor is used as input by utilizing the ADC inside the microcontroller and convert it to the speed. The speed measurement will be displayed on the LCD and it also displayed in the smartphone with wireless communication utilizing Wi-Fi baseband

Non Contact of Angular Speed Measurement Device

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5,0

€195,00 EUR

Project for Yana T.

Good communication, he did a great work eventhough im asking so much but he still can made it right. Even give me some suggestions for my project documentation.

C Programming

Electronics

Electrical Engineering

Arduino

+1 mais

Tasya A.

@tasyaarie

•

há 1 ano

5,0

$55,00 USD

Project for Yana T.

Great work, will hire him again.

C Programming

Electronics

Electrical Engineering

Arduino

+1 mais

Aleksandr K.

@aleksandrbraus

•

há 1 ano

5,0

$45,00 USD

CRC-7 FPGA Verilog Implementation

The work is done before the deadline. Communication and understanding of the issue is present. I would love to hire Yana again!

C Programming

Verilog / VHDL

Microcontroller

Electrical Engineering

FPGA

Oleg Z.

@zobovov

•

há 1 ano

Experiência

Microelectronics Center ITB

nov. 2019 - out. 2020 (11 meses, 2 dias)

IP Core Verification with Testbench, MATLAB and C. Some of the IP was verified are the IP for constructing the OFDM Architecture Model such as Convolution Encoder, Interleaver, Modulator, Synchronizer, Estimator and Equalizer, Demodulator, De-Interleaver and Viterbi Decoder Construct or Do the RTL Design of PAPR Architecture based on model in MATLAB Collaborate with other Researcher in a Team for doing RTL Integration on FPGA

AeroTerrascan

ago. 2019 - jan. 2020 (5 meses, 1 dia)

Construct Electro Optical (EO) Seeker using Multirotor (UAV) and do the Object Following. This Project utilizing OpenCV and OpenTLD Algorithm with Robot Operating System (ROS) to make the UAV Follow the Object that previously the Object was Selected by the Operator on Ground Control Station (GCS)

Schneider Electric

jun. 2018 - ago. 2018 (2 meses, 2 dias)

Doing some Automation Process Job such as Configuring the PLC and Construct HMI Design for Monitoring the Digital & Analog I/O Internal and Factory Acceptance Test using Current Injector on the PLC Baseplate and Monitor the Voltage / Current output in the Human Machine Interface (HMI)