Verilog fpga project trabalhos

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    9 verilog fpga project trabalhos encontrados, preços em USD

    ...i need a simple program that can calculate time (using hight precision timer, better in micro seconds) between 2 external triggers. Here can be useed FPGA Hardware for example (personaly i prefere FPGA for such task) Frequency range from 0,1 to 100 Hz to be tested. i have programm already done (see attachement), on my laptop i got only value for frequency

    $36 (Avg Bid)
    $36 Média
    4 ofertas

    The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

    $1345 (Avg Bid)
    $1345 Média
    13 ofertas

    This project write the Verilog to initialize and read frames from an image sensor with high quality through 8 LVDS. Requirements: Expert only for Verilog & validation simulation in Xilinx Vivado. I think you can finish this within a week if you are a Verilog expert. If you have experiences for this, please contact me sk [Removed by Freelancer

    $456 (Avg Bid)
    $456 Média
    8 ofertas

    I have a de1-soc fpga board ([fazer login para ver a URL]) for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.

    $35 (Avg Bid)
    $35 Média
    1 ofertas

    We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

    $40 / hr (Avg Bid)
    $40 / hr Média
    8 ofertas

    an expert on FPGA and Verilog should bid only...

    $160 (Avg Bid)
    $160 Média
    12 ofertas
    Verilog Design 3 dias left

    I have one architecture, needs the RTL verilog code for the design to be made and followed by placement and routing to derive the power.

    $138 (Avg Bid)
    $138 Média
    10 ofertas

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

    $115 (Avg Bid)
    $115 Média
    6 ofertas

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    $166 (Avg Bid)
    $166 Média
    7 ofertas