Assist with Implementation of VHDL design in an FPGA

SITUATION: I have a VHDL design for a custom processor + peripherals that needs to go into an FPGA. It passes functional simulation that uses VHDL testbenches. I am in the process of adding VHDL checkers. This design needs to pass timing simulation with a (soft) target frequency of 50 MHz, be programmed into an FPGA, and be verified using an off-the-shelf FPGA card. While I'm strong in digital design, VHDL coding and VHDL testbenches, I'm having trouble with vendor toolchains and documentation - I've spent a great deal of time with them, but have been blocked on key elements of the design flow, specifically constraints and timing simulations. A simple NDA will be needed before I can release the actual design files. DELIVERABLES NEEDED: recommended changes to the: -VHDL source code for the PLL and IOBs (pad ring functions) -project setup in the vendor's toolchain constraints file timing simulation run FPGA bitfile [Removed by Freelancer.com Admin for offsiting - please see Section 13 of our Terms and Conditions] to explain: -your process, starting with source code and ending in a working FPGA -the above items and how they were created -how to specify pad ring functions, e.g. registered output pads (i.e. IOBs) -other things I'm having trouble understanding from the vendor documentation