Quartus trabalhos

uni assignment using winCUPL, Altera’s QUARTUS II and AHDL. all discription needed is in the atached document. also needs to be Completed by monday.

uni assignment using winCUPL, Altera’s QUARTUS II and AHDL. all discription needed is in the atached document. also needs to be Completed by monday.

This should be very simple and easy project who is familiar with Altera DE2 board and it's interfaces. What I want is to integrate analog device AD73360 6-Channel ADC to the DE2 board through the GPIO pins. Download the datasheet from analog website. Basically you need to generate/interfa...Basically you will write Verilog (NOT VHDL) code to interface to the ADC and provide C functions/program that will run in the NIOS processor. Functions must be able to 1. Write all registers 2. Read all registers 3. Read values of all 6 channels and save them in 6 integers Sampling rate must be highest which is 64k for the ADC. ## Deliverables You will provide complete source, Quartus II 7.2 project files, NIOS EDS C++ code/project file and instruction to run and test on Al...

This is a straightforward project for anyone familiar with using the Altera DE 2 development board and the Quartus software.? The project is to help code a system using the drah and drop NIOS processor, read a voltage input, display using the lcd screen and drive a stepper output.? ? Coders who are familiar with vhdl, quartus and the altera cyclone 2 will find this very straightforward.

...having a trouble in chip design work. I want an program source code (in any programming language) that - Import any designs based on VHDL source code or netlist exported from Xilinx or Altera Development Tool (Quartus, ISE,...) - Parse and Implement any algorithm that will modify the design to give an new design which power consumpt is reduced - Certainly, output is the new power optimized netlist or VHDL source code that can be imported again to Quartus or ISE (xilinx). To prove that power consumption has been reduced in modified design, I will test base on power estimate tool of Quartus or ISE. Although these development tools have optimized power when synthesis but I want to do it myself. So you can use any algorthm that can optimize power such as RTL isolation, ...

Need to implement a 16Bit Calculator.. need to do the following Ops:- 1) ADD 2) SUB 3) AND 4) OR 5) XOR 6) BRANCH.. Inputs are 2 pushbuttons and 8 dipswitches.. Output is 2 7-segment display. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in r...the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platfor...

Need help to write a single cycle datapath for a elevator control system.. specifications: 1) 16bit instructions 2) 8bit datapath 3) 256x16 ROM 4) 256x8 RAM 5) 2 pushbuttons 6) 8 dipswitches ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in r...the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform ...

Wykonanie projektu w programie Quartus II (VHDL). Sygnalizacja pustego i pełnego bufora

I require a (Altera)NIOS II, CPU processor to be enhanced, i require the interrupt controller to support 32 UARTS and Interrupts from Timers,EPCS and the LAN. Ideally i require the system to have 36-38 Interrupts. Requirements. VHDL source for new Interrupt Controller Details of how to integrate into NIOS II and Quartus Example C Source for Setup of new controller. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installe...

...starting signal, a data ouput (estimate of e^tanx) as a 16 bit 2's complement #, and an output control signal to indicate the data output is available. This is to be designed in VHDL with a datapath of no more than 2 multipliers and 1 adder. I created all this on paper, but now I need help doing the VHDL and how to simulate it. I have some of the VHDL but not all----PLEASE HELP! I'm using Altera Quartus II. Here are my test cases: x = -1 or "1.0000000" x = -0.5 or "1.1000000" x = 0 or "0.0000000" x = 0.5 or "0.1000000" x = 0.9921875 or "0.1111111" x = 0.015625 or "0.0000010" ATTACHED ARE THE DIAGRAMS AND VHDL CODE I RAN! I NEED HELP MAKING IT WORK AND SIMULATING IT! I CAN GIVE U MORE ...

<> ## Deliverables complete design 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run conditio...platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform Altera Quartus II <>

I have many parts of one project, that need to be murged into one project in 2 days deadline. The language is VHDL, and the required tools are ModelSim and Quartus II. If you feel confident about these technologies, pre-bid. The details will be provided in private before the bidding is accepted.

Hello, Please, find the description in the file attached. Only the second part needs to be done. I will provide you with the diagrams needed from the first part. This is has to be completed in 2 days or less. Thanks. Etoso ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of a...platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform VHDL, Quartus II, Model...