LANGUAGE-VHDL

Use the structural abstraction level of VHDL to write the following program for the DE0 board. Write a VHDL program for a three-digit counter that repeatedly counts from 000 to 199 using seven-segment displays. The counter should have an active-low asynchronous reset input that resets the counter to 000. It should also have an active-low enable input. The counter will change values every 0.25 seconds if the inputs are set appropriately. Your program should use the following three components: 1. A counter that has one output that goes high once every 0.25 seconds. The output should stay high for one cycle of the 50 MHz clock. The counter should have enable, reset, and clock inputs. Use one instance of this component. 2. A four-bit counter that repeatedly counts from 0 to a maximum value. It will have a ripple carry output that will be set to 1 when the count is at the maximum value. The counter should have two active-high enable inputs, a reset input, and a clock input. Both enable inputs need to be high for the counter to be enabled. Use three instances of this component. 3. A four-bit to seven-segment display converter. Use three instances of this component. The active-low enable input to the three-digit counter should enable the 0.25 second counter. Use RTL for your program. Use the 50 MHz clock for all sequential circuits and use the enable inputs of the counters to control when the counters increment.