Verilog cleanup (simplification) & circuit schematic

I have some really old Verilog code that was generated from some obsolete hardware (~30 years old, specialized and no longer made). Unfortunately this recreation took into account numerous hops done for timing... so it's pretty messy. What I would like is for the Verilog code to be cleaned up without altering the gates (so equivalent logic, just removing the confusing hops). Typically you'll see lines like A<= B | C, B<=D, D<=E, E=F, F=G, G=H in the Verilog. So I'd like that simplified to just A<= H | C. I think their are programs that can do this, I just don't have access. The easiest way to work would be from the output backwards towards the inputs. I'd also like a circuit schematic as well, preferably in a format that is widely used. Again I know plenty of software will generate this from the Verilog so it shouldn't be to bad. I'm attaching a sample file I have 9 of these that need immediate fixing and will have about 20 more after the initial 9. So if you do well I'll rehire for phase 2. Anyone that can give me a sample of the attached so I can see that you can do the work will get top consideration for the work.