ashishshuklabs

Education Master of Science in Electrical Engineering University of Hawaii at Manoa graduated: 05/2008 Bachelor of Engineering in Electronics and Design Technology Nagpur University graduated: 08/2003 Technical Skills *C,C++, Perl and Tcl, Unix shell scripts *Hardware Description Language- Verilog and VHDL *MATLAB and Simulink, PSPICE, SwitcherCAD, Synopsis-Scirocco, Design Compiler *ModelSim, Xilinx ISE and Systems generator, Zealand IE3D *Familiarity with WCDMA, CDMA, Ethernet Technology *UNIX (Solaris, HP), Linux, Windows *Familiarity with MSSQL and Oracle *Testing tools: Mercury interactive’s Loadrunner, QTP and Quality Center Publication(s) *Ashish Shukla and Luca Macchiarulo, "FPGA Based ECG Analysis System", Proceedings of the Sixth IASTED International Conference on Biomedical Engineering, Pg 68-72, Innsbruck, Austria, February 13-15, 2008. *Ashish Shukla and Luca Macchiarulo, "Exploring and Prototyping Designs for Biomedical Applications", Excellence in Automotive and ISM, Pg 18-21, Xcell Journal, magazine by Xilinx Corp,Third Quarter of 2008. *Ashish Shukla and Luca Macchiarulo, “A Fast and Accurate FPGA based QRS Detection System”, 30th Annual International Conference of IEEE Engineering in Medicine and Biology Society(EMBS’08),Vancouver, British Columbia, Canada, Pg 4828-4831, Aug 20-24, 2008. Relevant Experience ***FPGA Implementation of real-time ECG Analysis Algorithms 01/07-02/08 Designed and implemented a one of a kind, real time ECG Analysis system on a Xilinx FPGA. The proposed FPGA based design can be used as a portable heart rate monitoring system, which could generate the ECG report of a patient in real time and cut down the delays present in the currently existing systems. Tasks performed include: **Software implementation of the ECG signal processing algorithm *Programmed and simulated the algorithm in MATLAB. *Tested the algorithm on a variety of test data and original data records. *Optimized the algorithm for accurate peak detection. **Conversion of the software implementation into hardware design *Described the RTL design in VHDL. *Closely matched and converted the floating point arithmetic functions to fixed point arithmetic for hardware implementation. *Implemented filtering stages and imported VHDL modules in Xilinx system generator environment. *Wrote test benches and carried out functional simulation in Modelsim and Simulink environment. *Performed static timing analysis (STA) and synthesis of the design using Xilinx ISE. *Optimized the design for an appropriate utilization of FPGA resources. *Proposed and added complex features in the design for increased accuracy. *Performed Hardware-in-the-loop simulation and testing using real data records and compared the results against real annotations. Tools Used: MATLAB and Simulink, Modelsim, Xilinx ISE, Xilinx System Generator, Xilinx Spartan 3E starter kit, oscilloscope *ASIC design - On-chip asynchronous communication scheme Designed a GALS (globally asynchronous locally synchronous) communication scheme for a prototype Network-on-chip application. Major task involved synchronizing data latching in multiple clock domains (transmitter and receiver). Module was designed in VHDL and simulated and tested with a basic 8-bit adder application. Synthesis was performed using design compiler. Tools Used: Modelsim, Scirocco and Design Compiler by Synopsys *ASIC design - Instruction Accurate RISC CPU Designed a reduced instruction set (RISC) CPU for a prototype mobile phone application. Implemented the design in VHDL and tested it with 6 instructions based on different addressing modes for 32 bit data. Functional simulation and synthesis was carried out using the synopsys tools. Tools Used: Modelsim, Scirocco and Design Compiler by Synopsys. *FPGA Design - High speed 10base-T Ethernet interface Implemented Ethernet full duplex data transfer connection on a Xilinx FPGA board. The 10base-T interface provided basic MAC functionality and PHY services and was used to establish high speed data transfer between the firmware connected to motor through the FPGA. Tools Used: Xilinx ISE and Modelsim. **Design Engineer Hoist Elevators (India) Pvt. Ltd, India 05/03-07/05 Initially worked as an intern and later continued as a full time Design Engineer. Responsibilities included *Testing the entire firmware to be integrated into the elevators. Carried out circuit design and simulation using PSPICE and SwitcherCAD. *Researched and Implemented the control logic of elevators and the induction motor on Pluto FPGA. The design included logic for elevator call control for various floor levels, control for the motor rotation and emergency power control. The design was implemented in VHDL and Modelsim and Altera Quartus was used for simulation, synthesis and design implementation. *Serial (RS 232) interface design Designed the transmitter and receiver sections for the serial interface (UART) on a Pluto FPGA board. The design was tested by passing 32 bit data at a standard baud rate of 115200. The interface was responsible for high speed data transfer between the power control circuit and the computer. *Oversaw commissioning and implemented testing and inspection procedures to ensure safety during normal operation for new elevators. *Extensively used Oscilloscopes for debugging and signal analysis. Tools Used: Xilinx ISE, Modelsim, Quartus II, Pspice, SwitcherCAD, Oscilloscope and Logic Analyzer Consulting Work **QA Automation and Performance Engineer EDS Corp.( an HP Company) Dublin, OH 11/08-Present Currently working as a QA automation Engineer for EDS, a Hewlett-Packard Development Company and deals with Department of Motor Vehicle Software Projects. Responsibilities Include: *Creating Automation scripts based on the functional test cases in C#. Extensively use Test Complete software for script creation and management. *Creating Loadrunner scripts for .Net framework based DMV client server application. Enhancing scripts by adding customized logic, Parameterization and Correlation. *Create performance test strategy and performance test scenario based on load statistics obtained from the stake holders. *Execute the load test scenarios for capacity, load and stress testing and analyze the server performance by monitoring different counters and transaction time for different requests. *Identify and convey to the development team, the bottleneck and suggest parameters for performance tuning. *Report to the Test Manager and the test team on a daily and weekly basis respectively. Environment: Windows 2003 server, Unix, Oracle, Apache, Weblogic, Quality Center and Loadrunner, C# **Quality Assurance Engineer Mass Mutual Financial Group Springfield, MA 06/08-10/08 Worked as a Performance Engineer for Cognos application implementation and upgrade at Mass Mutual Financial Group. Responsibilities include: *Project planning, scheduling and prioritization including setting up of Gantt chart to analyze and monitor the progress of multiple projects based on deadlines. *Plan and analyze test and work effort needed in the projects and set up project work matrix and time lines. *Work with Project Manager to gather and analyze user/business requirements and Project Architecture Documents and develop performance test strategy and performance test plan. *Create test cases with the involvement of development team and by analyzing the Sequence Diagrams and work flows. *Create test scripts based on the test cases in Performance Center (Web version of Loadrunner). *Carry out script enhancement by setting up rendezvous point, implementing parameterization and correlation to capture dynamic data returned from servers. *Set up multiple load test scenario based on the test strategy in Performance Center. *Carry out performance, stress and load testing in Performance Center. *Identify bottlenecks in the system by analyzing various graphs generated in Performance Center for the Apache, Weblogic, Websphere and Oracle servers and other underlying infrastructure. *Interact with developers, infrastructure and system teams in isolating bottlenecks and problem resolution. *Publish performance test results and analysis reports and upload them in Performance Center and an internal database. *Report to the respective Project Managers and Project Director for the team on a daily as well as weekly basis to set up goals and to inform them about the progress of the performance test effort. *Write SQL queries to check data integrity and create stored procedures and triggers. Environment: Windows 2003 server, Unix, DB2, Oracle, Apache, Websphere, Weblogic, MS office Project 2003, Performance Center, Quality Center and Loadrunner Other Experience/Projects **Teaching Assistant University of Hawaii 01/06-01/08 Taught C++ programming (CS-211) and MATLAB programming (PHY-170) course for the Department of Electrical Engineering and the Department of Physics and Astronomy respectively, at UH Manoa. Taught and managed over 150 students from varying backgrounds. **RF/Microwave - Microwave sensor for blood glucose monitoring Designed and simulated a prototype non-invasive sensor for blood glucose monitoring of diabetic patients using IE3D. The size of the spiral shaped radiating element of the sensor was less than 40 mm and had an operating frequency range between 0.5 – 2.5 GHz. Tools Used: MATLAB and IE3D by Zealand software **RF and EMI-Ray tracing model for improved radio wave propagation prediction Simulated a ray tracing model in MATLAB for predicting the amount of electromagnetic energy transfer from a source to target location for a prototype urban environment setting based on Manhattan architecture. Simulation performed for all the cases involving reflection, refraction and diffraction of the radio waves along their path, before reaching the target. Tools Used: MATLAB and Simulink Additional Information *Attended workshop by Xilinx Corp. on DSP design flow and porting of DSP applications using System Generator. *Experience in FPGA and ASIC design/development. *Experience writing and debugging VHDL code, prototype designing, Synthesis, Placement and Routing, Timing Closure, Debugging and handling multiple clock domain issues and Verilog to VHDL code conversion. *Extensive experience with CAD tools like Xilinx ISE, System Generator (DSP design), Modelsim, Synopsys tools Scirocco (simulator) and Design Compiler (synthesis), MATLAB and Simulink.