snake leader game

I have a lot of experienced in doing RTL Design with Verilog and Verification as well. I used to work as a Researcher at the OFDM Transciever group to make a lot of IP Core or module from Verilog. Previously i was done a project with verilog and the client from Russia to make CRC with 1 bit error correction based on the algorithm that the client gave to me and i have done it <24/7. The other one is i used to solve or do debugging inside the verilog code why the waveform is not equal as expectation. Hopefully my skill and experienced could fulfill this project's requirements. Thank You

Hello. I just read your job application and attached file. It is a relatively easy job so I can do it with a low price in a matter of days. Ofcource I can deliver it in less than a day but since it is an academic assignment I prefer to put some consideration into it to deliver a quiality code. Best regards

Hi buddy, Good that the homework still has time untill 28 Oct. I am free on my weekend, I could code it for you. BUT your budget is really insufficient :/ Although I guess you are a student and don't have much money, I used to do people's homework for at least $50 when I was a student back then. Which makes around 3740 rupees I guess. Lets make a discount and call it 3000, it's fine. If you have that budget I'd love to help you and finish your homework on time. Sorry that I cannot help further on the bid amount. You know, I will spend a lot of time for the project where I could work on something else with more profit. So If you feel okay, do not hesitate to contact me so we discuss the details. Have a nice and healty day.

Hello, This is for me because I have learn verilog and fpga design . I have verilog tools. I think this project best for me.

Hi, I am post graduate student in VLSI and currently working as a design engineer(Front end) in Application team. I had done many projects on FPGA ,written so many Verilog codes and my daily work is based on Verilog codes. I had gone through the attachment and sounds exciting. So, This is my piece of cake. Could delivery you the project . Reach out to me for other fix like deadlines, amount over chat. Regards, sreeja.

Hello, I am Digital Design Engineer. I have knowledge about FPGA and ASIC flow using Verilog/ VHDl. I have worked on similar projects to what you are looking for using verilog and vhdl. I would love to work on your project.