Xilinx Zynq 7020 - VHDL/Processor Application - Vivado 2019.1

I have Zc 702 board, and I have interface LiDAR kit with FPGA before. I can help you. ------------- Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and others. Please contact me to discuss more about this project. Kindest regards.

Hello I am not 100% clear of what you actually have at the moment. Have you written any code yourself? Or do you need all the FPGA code writing? You mention in your pdf that you need slides 5 to 7 developing. Is that the case? If you would like to discuss things then I would be happy to talk to you. I have just placed an initial bid and we can discuss costs. Regards Jon

doesn't seem like an easy task even for an electronics engineer anyway, i can help you but don't expect results from the first time, i need to read your attached document and some datasheets first, please only contact me if you are ready to create a milestone.

Summary • 20+ years of experience in development, test and verification of Embedded Systems • Expert knowledge in programming in C++ and C in embedded and application programming • Agile software development in a scrum team. Experience in OOA/OOD, Requirements Engineering and Testing. • Extensive experience in development and verification of digital systems (ASICs and FPGAs) • Experience with inter-chip and intra-chip communications standards and bus systems like Avalon, AMBA (AHB, APB, AXI), SPI, I2C. • Experience with microprocessor cores like NIOS, ARM Cortex-A9, TriCore, Xtensa, PIC. • Bring-up experience of complex embedded systems. • Branches experience: automotive, telecommunication, aerospace and software houses. Tools and Technologies • Programming languages and HDLs: C/C++, VHDL, Verilog, SystemC, Python, Perl, tcl, Ada95, Javascript • Libraries: OWL, STL, QT • Digital Design Tools: Quartus, Libero, ISE, Vivado, Questa, ModelSim, Design Compiler, RTL-Compiler, SoC Encounter, Apollo, Prime Time, Formality, NC-Verilog, Tetramax, HSPICE, Gnu-Make, Altium Designer, Eagle • Compilers and IDEs: gcc, Eclipse, Microsoft Visual Studio, gnu-Make, JBuilder, ObjectAda. • Debuggers: gdb, Universal Debug Engine (UDE) • RTOS: linux, eCos, Android • Lab Instruments: Hands-on experience with lab instruments like oscilloscopes, logic analyzers, signal generators. • Version-Control -Software: Subversion (svn), Microsoft TFS, Git

15 Years of experience in ASIC Design & Verification. Protocols - USB3.0, AHB, AXI, PCIe (8+ Years of Experience). FPGA - 5+ Years of Experience. Language - Verilog, VHDL & System Verilog (10+ Years of Experience). Verification - OVM & UVM (10+ Years of Experience).