Perl convert verilog vhdl trabalhos

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    10,057 perl convert verilog vhdl trabalhos encontrados, preços em USD

    Implementar um jogo em verilog ou vhdl em vga

    $140 (Avg Bid)
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    6 ofertas

    Jogo VGA em Verilog para FPGA

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    3 ofertas
    VHDL/verilog Encerrado left

    Segue trabalho em anexo

    $147 (Avg Bid)
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    10 ofertas
    Verilog e FPGA Encerrado left

    Implementar um JOGO mais simples possível com apenas os leds na linguagem verilog ou vhdl... Pode ser o jogo de decorar as cores dos leds que piscam, ou campo minado com leds, qualquer jogo simples (sem gráficos VGA.. projeto super simples na linguagem verilog).

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    Preciso de um projeto em Verilog que gerencie o consumo de água de uma residencia.

    $434 (Avg Bid)
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    2 ofertas
    Veriog Tomasulo Encerrado left

    Neste projeto você irá utilizar Verilog para implementar o algoritmo Tomasulo de despacho simples como descrito no livro texto (Seções 3.4 e 3.5). Descrição No algoritmo Tomasulo a execução das instruções é dividida em 3 estágios: despacho, execução e write back. Esses três está...

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    Preciso fazer um hardware com FPGA Altera ou Spartan da Xilinix programado em VHDL. Ele precisa receber e enviar pacotes UDP de um computador através da porta Ethernet. Eu já tenho o software que faz o envio dos pacotes UDP, hoje eu uso um hardware com FPGA Spartan III, pronto comprado da China. O hardware e o software que roda no computador são

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    Contrata-se programador perl ou python para atualização de uma ferramenta de captuda de links http:// de sites por exemplo o script entra no [fazer login para ver a URL] verica o codigo fonte da página e extrai todos os link que ali tiver e guarda em um banco de dados a ferramenta está OK mais precisa de uma atulização.

    $448 (Avg Bid)
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    Tenho um sistema web em cgi (Perl) mas estou sem programador. Gostaria fazer algumas modificações nele, adicionando mais campos em um formulário, gravando estas opções em arquivo texto e executando comandos no sistema Linux. Interessados, enviar propostas!

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    Precisamos de um desenvolvedor freelancer em Perl e um Phyton, possuímos demandas. Estamos em crescimento, precisamos de profissionais que trabalhem bem,  sejam responsáveis e que possuam experiência. Interessados, enviar propostas!  

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    ...para formar uma palavra de 32 bits. Os sinais de controle m1, m2, m3, wPC, wMem, wRI devem ser associados às chaves de entrada. Um arquivo comprimido com todos os módulos VHDL do MIPS multiciclo é disponibilizado no Moodle. O código MIPS a ser carregado na memória está contido no arquivo mem.mif. Para exibição dos dados nos ...

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    Preciso fazer a migração de um sistema web desenvolvido em Perl para um novo servidor.

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    Preciso de código em VHDL e respectivos ficheiros de testbench para um relógio digital. No LCD deve de aparecer: Linha 1: HH:MM:SS Linha 2: Relógio PNL Horas (HH) de 00 a 23 Com possibilidade de acerto Placa com frequência de relógio de 50Mhz Placa onde irá funcionar Xilinx/ Diligent Sparten-3E Preciso do có...

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    PHP, Perl Encerrado left

    Estamos buscando un Desarrollador PHP, PERL para un trabajo de una o dos semanas. Indispensable experiencia comprobable. - Lenguajes de Programación: PHP - Habilidades adicionales: PERL, XYMON <span style="line-height: 1.6em;">- 3-5 años de experiencia en programación.</span>  

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    ...-Programming Language : Verilog HDL. -This project is divided to two parts:- Part 1. Design and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x

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    General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Ba...

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    verilog counter 5 dias left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

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    Here projects are implemented in VHDL programming using Xilinx software. B.E/[fazer login para ver a URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

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    fix perl code 4 dias left

    fix perl code project .Good skills in perl required

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    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [fazer login para ver a URL] file.

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $753 (Avg Bid)
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    1 ofertas

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit

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    ...this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals and

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    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

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    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

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    You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

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    We need a very simple script in perl which can identify bracket balancing for a string of line. It can display the index where the bracket is not balanced or any syntax error.

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    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

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    I have 2 data files, one is a CSV with a unique ID. The other is a master dat...master data file that is pipe delimited. I need to match 2 fields in each of the data files, and pull the record from the pipe delimited file. Please quote to setup create a perl script that will do everything quoted above. Any questions, please don't hesitate to ask.

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    I'm looking for a PERL expert which is able to modify the script "xFileSharing", in order to provide a way to add the downloader's IP address into the generated file's metadata and/or into any other read-only data and guide us into doing it on our side. xFileSharing has to be already owned by the freelancer who is willing to complete this task, as

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    Vivado Expert Encerrado left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

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    Perl Scripting Encerrado left

    Perl scripting Perl scripting Perl scripting

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    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

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    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

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    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

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    1 ofertas

    Unser Webauftritt ist eine Eigenentwicklung in der Scriptsprache PERL und unter [fazer login para ver a URL] zu erreichen. Wir bieten Händlern die Möglichkeit auf unserer Plattform einen Online-Shop zu eröffnen. Manche Leistungen müssen deshalb intern bei uns zugebucht werden. Zur Zahlung dieser Leistungen (wie Z.b. Premium Tools) haben wir bereits

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    ...chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

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    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

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    Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL

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    Need VHDL expert Encerrado left

    I have a VHDL code. Then It has some issue. I need to fix it within a few hours. If you are electronic expert you can do it within 1 hours. I'll send details via interviewing. Ivan.

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    Hi there, I need a simple script (php/python or perl) that will make a POST request with an email address from an input file. Based on the response , I need to save/discard the email address. If you need more info, contact me please.

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    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

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    Need to convert an perl script to python

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